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Central processing unit
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561	Imperial College London Department of Computing Add to Reading List Source URL: www.doc.ic.ac.uk Language: English - Date: 2009-10-22 13:42:54 Computer memory Instruction set architectures Central processing unit Assembly languages Minicomputers Memory address Addressing mode Motorola 68000 CPU cache Computer architecture Computer hardware Computing
562	Are Your Passwords Safe: Energy-Efficient Bcrypt Cracking with Low-Cost Parallel Hardware Katja Malvoni (kmalvoni at openwall.com) Add to Reading List Source URL: www.usenix.org Language: English - Date: 2014-11-11 15:42:08 Cryptographic software System software Instruction set architectures Password Crypt John the Ripper ARM architecture Central processing unit Field-programmable gate array Software Computer architecture Bcrypt
563	The Numerical Algorithms Group Combining mathematics and technology for enhanced performance Contribution to the Panel Discussion Dr Stef Salvini Add to Reading List Source URL: www.compunity.org Language: English - Date: 2007-10-15 03:40:51 Application programming interfaces Parallel computing CPU cache Cache Central processing unit Computer memory Data center OpenMP Computing Concurrent computing Computer programming
564	Multi-threaded Performance Pitfalls 1 Multi-threaded Performance Pitfalls Ciaran McHale Add to Reading List Source URL: www.ciaranmchale.com Language: English - Date: 2008-05-17 08:17:25 Central processing unit Microprocessors Parallel computing Computer memory Threads Scalability Multi-core processor CPU cache Cache Computing Concurrent computing Computer hardware
565	Microsoft Word - Arch_WhitePaperB2 _2__6_12_09.doc Add to Reading List Source URL: www.chipwrights.com Language: English - Date: 2009-10-01 18:55:24 Electronic engineering Datapath Register file Instruction set ARM architecture Accumulator Processor register Memory address No instruction set computing Computer architecture Central processing unit Computer hardware
566	Learning Bayesian Networks for Improved Instruction Cache Analysis Mark Bartlett, Iain Bate and James Cussens Department of Computer Science University of York Heslington, York, UK Add to Reading List Source URL: www.cs.york.ac.uk Language: English - Date: 2012-05-02 15:17:24 Computer hardware Computer architecture Central processing unit Bayesian network Networks CPU cache Worst-case execution time Graphical model Cache Statistics Bayesian statistics Statistical models
567	C8051F120C8051F130Mixed Signal ISP Flash MCU Family Analog Peripherals - 10 or 12-bit SAR ADC Add to Reading List Source URL: gdansk.bradley.edu Language: English - Date: 2015-02-19 03:04:54 Computer architecture Integrated circuits IBM PC compatibles Central processing unit Intel MCS-51 I²C Universal asynchronous receiver/transmitter Serial Peripheral Interface Bus TI MSP430 Microcontrollers Electronics Electronic engineering
568	ARM 7TDMI Data Sheet Issued: August 1995 Copyright Advanced RISC Machines Ltd (ARMAll rights reserved Add to Reading List Source URL: www.ndsretro.com Language: English - Date: 2006-12-01 15:44:11 Central processing unit Instruction set architectures ARM architecture Embedded systems ARM7 Instruction set Joint Test Action Group Reduced instruction set computing Microprocessor Computer architecture Computer hardware Electronic engineering
569	Prefetching and Cache Management Using Task Lifetimes Vassilis Papaefstathiou∗ Manolis G.H. Katevenis∗ FORTH-ICS Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2014-02-26 04:38:59 Computer memory Cache Central processing unit Microprocessors CPU cache Prefetcher Multi-core processor Microarchitecture X86 Computer hardware Computing Computer architecture
570	OMP AMMP analysis with Sun ONE Studio 8 Add to Reading List Source URL: www.compunity.org Language: English - Date: 2007-10-15 03:40:55 Computer programming OpenMP Thread Central processing unit Lock Lis Barrier Computing Parallel computing Software

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